SCLL

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Interpret as SCLL

Description

SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.

Fields

SCLL	Count for SCL low time period selection.
RESERVED	Reserved. The value read from a reserved bit is not defined.

Links

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